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Gujarat Technological UniversityWinter 2024 Examination

GTU 3130704 Digital Fundamentals (DF) Winter 2024 Paper Solution & PDF

B.E. · Computer Engineering · Semester 3 · Subject Code: 3130704
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Total Marks70 MarksExternal theory exam
Passing Marks23 Marks33% minimum cutoff
Exam Duration2.5 Hours10:30 AM – 1:00 PM
Paper Structure5 QuestionsWith internal OR choices
Jump toQ1Q2Q3Q4Q5

Question 1

14 MarksMedium
(a)
aPerform the following mathematical operations using 2’s complement method.
i)(9)10 + (-5)10
ii)(3)10 –
8)10
3 Marks
(b)
State and prove De-Morgan’s theorems using truth-tables.
4 Marks
(c)
Explain the characteristics of Digital ICs.
7 Marks

Question 2

14 MarksMedium
(a)
Design a Full Adder circuit using basic logic gates.
3 Marks
(b)
Design a modulo-6 ripple counter using T-Flip-flops.
4 Marks
(c)
Design a 4-bit Binary to Gray Code Converter using K-map.
7 Marks
OR OPTION
(c)
Draw a two input TTL NAND gate and explain its operation.
7 Marks

Question 3

14 MarksMedium
(a)
Explain Race Around Condition in JK flip flop.
3 Marks
(b)
Design a 1 - bit Magnitude Comparator.
4 Marks
(c)
Explain Hamming codes for error correction with a suitable example.
7 Marks
OR OPTION
(a)
Find expression for the following and implement using logic gates.

F(A,B,C,D) = πM(0,2,3,6,7,8,9,12,13)

3 Marks
(b)
Implement D flip flop using JK flip flop.
4 Marks
(c)
Design a 4-bit twisted Ring Counter using JK flip flops.
7 Marks

Question 4

14 MarksMedium
(a)
Differentiate Synchronous Counters and Asynchronous Counters.
3 Marks
(b)

Implement the following using 8:1 MUX. F = f(A,B,C,D) = Σm(2,4,5,7,10,14)

4 Marks
(c)
Design a synchronous BCD counter using J-K flip-flops.
7 Marks
OR OPTION
(a)
Implement full subtractor using 3:8 decoder and write a truth table.
3 Marks
(b)
Explain the specifications of Digital to Analog Converters.
4 Marks
(c)
Explain Successive Approximation type A/D converter.
7 Marks

Question 5

14 MarksMedium
(a)
Differentiate Static RAM and Dynamic RAM.
3 Marks
(b)
Write a short note on FPGA.
4 Marks
(c)
Explain the operation of Dual-slope A/D converter.
7 Marks
OR OPTION
(a)
Explain basic structure of a CCD (Charge Coupled Device).
3 Marks
(b)
Write a short note on Programmable Array Logic.
4 Marks
(c)
Explain various types of Read Only Memory.
7 Marks
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About this Examination Paper & Attribution

Official Gujarat Technological University (GTU) examination paper and step-by-step solutions for Digital Fundamentals (DF) (Winter 2024, B.E. · Computer Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

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