Question 1
(a)
List out various logic families. Also list characteristics of digital IC.
3 Marks
(b)
State and prove De-Morgan’s theorems using truth-tables.
4 Marks
(c)
Implement AND, OR, EX-OR gates using NAND & NOR gates.
7 Marks
Gujarat Technological UniversitySummer 2024 Examination
GTU 3130704 Digital Fundamentals (DF) Summer 2024 Paper Solution & PDF
B.E. · Computer Engineering · Semester 3 · Subject Code: 3130704
Total Marks70 MarksExternal theory exam
Passing Marks23 Marks33% minimum cutoff
Exam Duration2.5 Hours10:30 AM – 1:00 PM
Paper Structure5 QuestionsWith internal OR choices
Question 2
(a)
Reduce the expression F = x’y’z +yz+ xz
3 Marks
(b)
Convert the decimal Number 330.5 to base 4 and base 8.
4 Marks
(c)
Design a Combinational circuit that convert Binary to BCD code converter.
7 Marks
OR OPTION
(c)
Design a Combinational circuit that convert BCD to Excess 3 code converter.
7 Marks
Question 3
(a)
Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 1, 3, 5,6, 7, 10, 13,14, 15)
3 Marks
(b)
Explain 4 – bit parallel adder with diagram.
4 Marks
(c)
Design 2 - Bit Magnitude Comparator.
7 Marks
OR OPTION
(a)
Design D FF using SR FF. Write truth table of D FF.
3 Marks
(b)
Minimize following Boolean function using K-map: F(A,B,C,D) = Σ m(1, 5, 6, 12, 13, 14) + d(2, 4)
4 Marks
(c)
Design 3-bit even parity generator circuit.
7 Marks
Question 4
(a)
Compare static RAM and dynamic RAM.
3 Marks
(b)
Explain JK flip flop with its characteristic table and excitation table.
4 Marks
(c)
Write a brief note on race around condition and its solution. Draw & explain the logic diagram of master-slave JK flip-flop.
7 Marks
OR OPTION
(a)
Explain the types of ROM.
3 Marks
(b)
Explain Look-ahead Carry generator
4 Marks
(c)
Design a Synchronous counter with the following binary sequence: 0, 1, 3, 4,5, 7 and repeat. Use T – flip-flops
7 Marks
Question 5
(a)
Explain the working of a Counter.
3 Marks
(b)
Explain R-2R ladder type D/A converter
4 Marks
(c)
A combinational circuit is defined by the function F1 (A, B, C,) = Σ m (0,1,3,4) F2 (A, B, C,) = Σ m (1.2.3,4,5) Implement the circuit with a PLA having 3 inputs, 3 product term & 2 outputs.
7 Marks
OR OPTION
(a)
Explain the working of SISO shift register.
3 Marks
(b)
Explain the specification of D/A converter
4 Marks
(c)
Describe operation of D/A converter with binary-weighted resisters
7 Marks
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About this Examination Paper & Attribution
Official Gujarat Technological University (GTU) examination paper and step-by-step solutions for Digital Fundamentals (DF) (Summer 2024, B.E. · Computer Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.