Gujarat Technological UniversitySummer 2026 Examination

GTU 3130704 Digital Fundamentals (DF) Summer 2026 Paper Solution & PDF

B.E. · Computer Engineering · Semester 3 · Subject Code: 3130704
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Total Marks70 MarksExternal theory exam
Passing Marks23 Marks33% minimum cutoff
Exam Duration2.5 Hours2:30 PM – 5:00 PM
Paper Structure5 QuestionsWith internal OR choices
Jump toQ1Q2Q3Q4Q5

Question 1

14 MarksMedium
(a)

Convert the decimal number 163 to its equivalent binary, octal and hexadecimal forms.

3 Marks
(b)
Convert the BCD number 10010111 into its equivalent decimal and Excess-3 code.
4 Marks
(c)

What do you mean by universal gates, and which gates are universal? Convert NAND gate to OR gate. Convert NOR gate to AND gate.

7 Marks

Question 2

14 MarksMedium
(a)
Define : priority encoder, SOP and POS
3 Marks
(b)

Analyze the conditions for a 'Don't Care' term in K-map simplification and simplify the expression F(W,X,Y,Z)=∑m(1,3,7,11,15) with Don't Care d(W,X,Y,Z)=∑d(0,2,5).

4 Marks
(c)
Design a full subtractor circuit using basic logic gates. Also write its truth table.
7 Marks
OR OPTION
(c)
Implement a 4×16 decoder using two 3×8 decoders.
7 Marks

Question 3

14 MarksMedium
(a)

Distinguish between synchronous and asynchronous (ripple) counters based on their clocking mechanism.

3 Marks
(b)
Define the term : 'state table' for a sequential circuit, ripple counter
4 Marks
(c)
Draw a neat diagram of a 4-bit right shift register and explain its operation
7 Marks
OR OPTION
(a)

Analyze the state transition diagram for a Johnson (twisted ring) counter and explain its counting sequence for 4 flip-flops.

3 Marks
(b)

Define the term 'ring counter' and briefly explain how it differs from a Johnson counter.

4 Marks
(c)
Explain J-K flip-flop and T flip-flop along with diagram and excitation table.
7 Marks

Question 4

14 MarksMedium
(a)

Compare the weighted resistor D/A converter with the R-2R ladder D/A converter based on complexity, accuracy and ease of expansion.

3 Marks
(b)
Define the term 'Quantization' and 'Encoding' in the context of A/D conversion.
4 Marks
(c)

Evaluate the advantages and disadvantages of the dual slope A/D converter compared to the Successive Approximation A/D converter

7 Marks
OR OPTION
(a)

Describe the operation of a Successive Approximation A/D (SAR) converter and state its main specification regarding conversion time.

3 Marks
(b)
List the main components of an Analog-to-Digital conversion process
4 Marks
(c)

Justify the use of an R-2R ladder network over a weighted resistor network for high- resolution D/A converters. Evaluate the advantages and disadvantages of the both.

7 Marks

Question 5

14 MarksMedium
(a)
Define Read Only Memory (ROM) and list its different types.
3 Marks
(b)
Describe the architecture and use of Field Programmable Gate Arrays (FPGAs).
4 Marks
(c)

Design a simple combinational logic function F(A,B,C)=∑m(0,1,2,5,7) and implement it using a Programmable Logic Array (PLA), clearly showing the internal connections.

7 Marks
OR OPTION
(a)
Differentiate between static RAM (SRAM) and dynamic RAM (DRAM).
3 Marks
(b)
Describe the concept of memory organization in semiconductor memories
4 Marks
(c)

Implement the logic function F(X,Y,Z)=∑m(1,2,4,7) using a ROM as a PLD, showing the memory organization.

7 Marks
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About this Examination Paper & Attribution

Official Gujarat Technological University (GTU) examination paper and step-by-step solutions for Digital Fundamentals (DF) (Summer 2026, B.E. · Computer Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

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