Gujarat Technological UniversitySummer 2026 examination

GTU 3130704 Digital Fundamentals (DF) Summer 2026 Question Paper & PDF

B.E. · Computer Engineering · Semester 3 · Subject code 3130704
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Total
70 marks
To pass
23 marks (33%)
Duration
2.5 Hours 2:30 PM – 5:00 PM
Questions
5 with internal choice
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10 of 25 questions on this paper were also asked in other years. 4 more are types of question GTU sets again with new data. Each is marked below with the years it appeared.See all 31 repeated 3130704 questions, most asked first

Q.1

14 Marks
(a)
3 marksSame type asked in 4 of 6 papers

Convert the decimal number 163 to its equivalent binary, octal and hexadecimal forms.

Also asked in Winter 2025 Q1b, Summer 2024 Q2b, Summer 2023 Q1b

(b)
4 marks
Convert the BCD number 10010111 into its equivalent decimal and Excess-3 code.
(c)
7 marksAsked in 3 of 6 papers

What do you mean by universal gates, and which gates are universal? Convert NAND gate to OR gate. Convert NOR gate to AND gate.

Also asked in Summer 2025 Q1c, Summer 2023 Q1c

Q.2

14 Marks
(a)
3 marks
Define : priority encoder, SOP and POS
(b)
4 marksSame type asked in 3 of 6 papers

Analyze the conditions for a 'Don't Care' term in K-map simplification and simplify the expression F(W,X,Y,Z)=∑m(1,3,7,11,15) with Don't Care d(W,X,Y,Z)=∑d(0,2,5).

Also asked in Summer 2024 Q3b OR, Summer 2023 Q2b

(c)
7 marks
Design a full subtractor circuit using basic logic gates. Also write its truth table.
(c)
7 marksAsked in 2 of 6 papers
Implement a 4×16 decoder using two 3×8 decoders.

Also asked in Winter 2025 Q4b OR

Q.3

14 Marks
(a)
3 marksAsked in 3 of 6 papers

Distinguish between synchronous and asynchronous (ripple) counters based on their clocking mechanism.

Also asked in Winter 2025 Q3a OR, Winter 2024 Q4a

(b)
4 marks
Define the term : 'state table' for a sequential circuit, ripple counter
(c)
7 marksAsked in 3 of 6 papers
Draw a neat diagram of a 4-bit right shift register and explain its operation

Also asked in Summer 2025 Q4c, Summer 2023 Q3b

(a)
3 marksAsked in 3 of 6 papers

Analyze the state transition diagram for a Johnson (twisted ring) counter and explain its counting sequence for 4 flip-flops.

Also asked in Winter 2024 Q3c OR, Summer 2023 Q3c

(b)
4 marks

Define the term 'ring counter' and briefly explain how it differs from a Johnson counter.

(c)
7 marks
Explain J-K flip-flop and T flip-flop along with diagram and excitation table.

Q.4

14 Marks
(a)
3 marks

Compare the weighted resistor D/A converter with the R-2R ladder D/A converter based on complexity, accuracy and ease of expansion.

(b)
4 marks
Define the term 'Quantization' and 'Encoding' in the context of A/D conversion.
(c)
7 marks

Evaluate the advantages and disadvantages of the dual slope A/D converter compared to the Successive Approximation A/D converter

(a)
3 marksAsked in 4 of 6 papers

Describe the operation of a Successive Approximation A/D (SAR) converter and state its main specification regarding conversion time.

Also asked in Summer 2025 Q5b OR, Winter 2024 Q4c OR, Summer 2023 Q4c OR

(b)
4 marks
List the main components of an Analog-to-Digital conversion process
(c)
7 marks

Justify the use of an R-2R ladder network over a weighted resistor network for high- resolution D/A converters. Evaluate the advantages and disadvantages of the both.

Q.5

14 Marks
(a)
3 marksAsked in 4 of 6 papers
Define Read Only Memory (ROM) and list its different types.

Also asked in Winter 2025 Q5c OR, Winter 2024 Q5c OR, Summer 2024 Q4a OR

(b)
4 marksAsked in 4 of 6 papers
Describe the architecture and use of Field Programmable Gate Arrays (FPGAs).

Also asked in Winter 2025 Q5c, Summer 2025 Q5a OR, Winter 2024 Q5b

(c)
7 marksSame type asked in 4 of 6 papers

Design a simple combinational logic function F(A,B,C)=∑m(0,1,2,5,7) and implement it using a Programmable Logic Array (PLA), clearly showing the internal connections.

Also asked in Summer 2025 Q5c, Summer 2024 Q5c, Summer 2023 Q5b

(a)
3 marksAsked in 5 of 6 papers
Differentiate between static RAM (SRAM) and dynamic RAM (DRAM).

Also asked in Winter 2025 Q5a, Winter 2024 Q5a, Summer 2024 Q4a, Summer 2023 Q5a OR

(b)
4 marksAsked in 2 of 6 papers
Describe the concept of memory organization in semiconductor memories

Also asked in Summer 2023 Q5c

(c)
7 marksSame type asked in 3 of 6 papers

Implement the logic function F(X,Y,Z)=∑m(1,2,4,7) using a ROM as a PLD, showing the memory organization.

Also asked in Summer 2025 Q5b, Summer 2023 Q5b OR

More Digital Fundamentals papers

Questions repeat across sessions. Working through two or three papers shows you which topics GTU asks most.

Winter 202570 marks · 5 questions
Summer 202570 marks · 5 questions
Winter 202470 marks · 5 questions
Summer 202470 marks · 5 questions

Other Semester 3 subjects

BE Computer

130001
Mathematics-III
3130004
Effective Technical Communication
3130006
Probability and Statistics
3130702
Data Structures

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About this paper

Official Gujarat Technological University (GTU) examination paper for Digital Fundamentals (DF) (Summer 2026, B.E. · Computer Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

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