GTU · BE Computer · Semester 4

GTU 3140707 Computer Organization & Architecture (COA) Old Question Papers PDF

Official Gujarat Technological University (GTU) old question papers PDF (Regular & Remedial) and step-by-step solved questions for Computer Organization & Architecture (COA) across 2023 – 2026 examinations.

7 papers, 2023 – 202670 marks23 to pass2.5 hours
37 questions GTU asked more than onceAsked in 6 of 7 papers: Discuss addressing modes of instructions.See list

Exam papers

Most repeated questions

37 questions GTU set in two or more of 7 papers, most repeated first. Tap a year to open that paper at the question.

  1. Discuss addressing modes of instructions.

    7 marksAsked in 6 of 7 papers

    Summer 2026 Q3c Winter 2025 Q3c Summer 2025 Q3b OR Winter 2024 Q4a Summer 2024 Q3c Summer 2023 Q1c

  2. What are different architectures as suggested by Flynn’s taxonomy?

    3 marksAsked in 5 of 7 papers

    Summer 2026 Q5a OR Winter 2025 Q3a Summer 2025 Q5c OR Summer 2024 Q3b OR Summer 2023 Q3a

  3. Discuss the associative memory.

    7 marksAsked in 4 of 7 papers

    Summer 2026 Q2c Winter 2024 Q5b OR Summer 2024 Q4a Summer 2024 Q4a OR Summer 2023 Q3c OR

  4. List various cache mappings. Explain any one in detail.

    7 marksAsked in 4 of 7 papers

    Winter 2025 Q5c Winter 2024 Q4c Summer 2024 Q4c Summer 2023 Q5c OR

  5. Explain address sequencing in the micro programmed control unit

    4 marksAsked in 4 of 7 papers

    Winter 2025 Q3b OR Summer 2025 Q4a OR Winter 2024 Q3b Winter 2023 Q2a

  6. Differentiate RISC and CISC architecture.

    3 marksAsked in 4 of 7 papers

    Winter 2025 Q2a Summer 2025 Q5b OR Winter 2024 Q3c Summer 2023 Q5b OR

  7. What is the cache coherence? What is the solution to cache coherence problem?

    3 marksAsked in 4 of 7 papers

    Winter 2025 Q5a Winter 2024 Q5c OR Summer 2024 Q5c Summer 2023 Q5c

  8. List the names of registers within a basic computer.

    3 marksAsked in 4 of 7 papers

    Summer 2026 Q2a Summer 2025 Q3a Winter 2024 Q1b Summer 2023 Q1a

  9. What is an interrupt? Explain interrupt cycle with flowchart.

    7 marksAsked in 3 of 7 papers

    Winter 2025 Q2c OR Summer 2025 Q3c OR Summer 2024 Q5b OR

  10. Compare tightly coupled and loosely coupled multiprocessors.

    4 marksAsked in 3 of 7 papers

    Winter 2025 Q5b Winter 2024 Q5a OR Summer 2024 Q5a

Show 27 more repeated questionsHide the 27 more
  1. Draw only the flowchart for Booths’ multiplication algorithm.

    4 marksAsked in 3 of 7 papers

    Summer 2026 Q5b OR Winter 2025 Q4c Winter 2023 Q1c

  2. List all the major difficulties in pipeline and briefly explain any one

    3 marksAsked in 3 of 7 papers

    Winter 2025 Q3a OR Winter 2024 Q3a Summer 2023 Q3a OR

  3. Explain memory reference instructions of ‘Basic Computer’.

    7 marksAsked in 2 of 7 papers

    Winter 2024 Q1c Summer 2024 Q2b

  4. Explain register stack and memory stack organizations.

    7 marksAsked in 2 of 7 papers

    Winter 2024 Q2c Summer 2024 Q3b

  5. Explain the sequence of asynchronous data transfer.

    7 marksAsked in 2 of 7 papers

    Summer 2026 Q4c OR Summer 2025 Q5c

  6. Discuss various characteristics of multiprocessor system.

    7 marksAsked in 2 of 7 papers

    Summer 2026 Q5c Winter 2025 Q5a OR

  7. Explain any three multiprocessor interconnection structures.

    7 marksAsked in 2 of 7 papers

    Winter 2024 Q5c Winter 2023 Q5c OR

  8. Why is the virtual memory? Explain the address mapping in detail.

    7 marksAsked in 2 of 7 papers

    Winter 2025 Q5c OR Winter 2024 Q4c OR

  9. Explain paging and address translation with example.

    7 marksAsked in 2 of 7 papers

    Summer 2024 Q4c OR Winter 2023 Q2c OR

  10. Explain micro programmed control organization in detail.

    7 marksAsked in 2 of 7 papers

    Summer 2024 Q2c Summer 2023 Q4c OR

  11. Explain first pass of an assembler with flowchart.

    7 marksAsked in 2 of 7 papers

    Summer 2024 Q5c OR Summer 2023 Q3b

  12. Discuss various memory hierarchies.

    7 marksAsked in 2 of 7 papers

    Winter 2023 Q2c Summer 2023 Q4a OR

  13. Describe the control unit of the basic computer with block diagram.

    7 marksAsked in 2 of 7 papers

    Winter 2025 Q2c Summer 2025 Q2c OR

  14. Write three address and two address instructions program for the following arithmetic expression. Discuss advantages and limitations of both types of programs. X = (A * B / C) + (D / E)

    7 marksSame type asked in 2 of 7 papers

    Winter 2024 Q2c OR Summer 2023 Q2c

  15. Write short note on the DMA.

    4 marksAsked in 2 of 7 papers

    Winter 2025 Q4b Summer 2023 Q4a

  16. Explain three state bus buffer.

    4 marksAsked in 2 of 7 papers

    Summer 2025 Q1b Summer 2023 Q3b OR

  17. Explain instruction format with its types.

    4 marksAsked in 2 of 7 papers

    Summer 2025 Q2b Summer 2024 Q1b

  18. What are status register bits? Draw and explain the block diagram showing all status registers.

    4 marksAsked in 2 of 7 papers

    Summer 2025 Q5b Summer 2023 Q5b

  19. State various phases of instruction cycle.

    4 marksAsked in 2 of 7 papers

    Summer 2025 Q3b Summer 2024 Q1c

  20. What is Memory Interleaving?

    3 marksAsked in 2 of 7 papers

    Summer 2025 Q5a OR Summer 2024 Q3a OR

  21. Write a short note on SIMD array processor.

    3 marksAsked in 2 of 7 papers

    Winter 2024 Q3a OR Summer 2023 Q4b

  22. Explain register stack.

    3 marksAsked in 2 of 7 papers

    Summer 2025 Q4a Summer 2024 Q2c OR

  23. Explain source-initiated asynchronous data transfer using handshaking.

    3 marksAsked in 2 of 7 papers

    Winter 2025 Q4a OR Winter 2024 Q4b OR

  24. Briefly explain the Daisy-Chaining priority.

    3 marksAsked in 2 of 7 papers

    Winter 2025 Q4a Winter 2024 Q5b

  25. Differentiate static RAM and Dynamic RAM.

    3 marksAsked in 2 of 7 papers

    Winter 2024 Q5a Summer 2024 Q4b OR

  26. Draw block diagram for 4-bit adder – subtractor.

    3 marksAsked in 2 of 7 papers

    Winter 2024 Q2a Winter 2023 Q3c OR

  27. Explain the Register Transfer Language with block diagram.

    3 marksAsked in 2 of 7 papers

    Summer 2025 Q1a Summer 2024 Q1a

Which branches take this subject

GTU's syllabus lists 3140707 for 5 branches. One set of papers serves all of them.

Semester 4: 5 branches

Computer Engineering, Computer Science & Design, Computer Science & Engineering, Information & Communication Technology, Information Technology

Other Semester 4 subjects

Common questions

Are these GTU 3140707 Computer Organization & Architecture papers valid for both Regular and Remedial exams?

Yes. Gujarat Technological University (GTU) follows the same 70-mark syllabus, exam blueprint, and 23-mark passing cutoff for both Regular and Remedial (ATKT/backlog) examinations. All 7 past exam sessions (2023 – 2026) serve as comprehensive preparation for either attempt.

How can I download GTU 3140707 Computer Organization & Architecture old question papers PDF?

You can download official GTU 3140707 original question paper PDFs directly from the table above with 1 click and zero deceptive ads or wait timers. Every paper also includes interactive online questions with AI study prompts.

What is the passing mark for GTU Computer Organization & Architecture (3140707)?

The external theory exam carries 70 marks. The minimum passing cutoff is 23 marks (33%). Exam duration is 2.5 hours.

What is the GTU exam pattern for 3140707?

The examination contains 5 main questions of 14 marks each, totaling 70 marks. Questions 2 through 5 provide internal OR choices, typically split into 3-mark, 4-mark, and 7-mark questions.