Gujarat Technological UniversityWinter 2025 examination

GTU 3131102 Digital System Design Winter 2025 Question Paper & PDF

B.E. · EC Engineering · Semester 3 · Subject code 3131102
Download official PDFView PDF here
Share with your class
Total
70 marks
To pass
23 marks (33%)
Duration
2.5 Hours 10:30 AM – 1:00 PM
Questions
5 with internal choice
No solutions on this paper yetNeed them for your exam? Ask once. Papers that students ask for are solved first, and we aim to add them within 24 hours.

Q.1

14 Marks
(a)
3 marks

Perform following subtraction using 2’s complement method. (11010)2 – (10000)2

(b)
4 marks
State & prove De Morgan’s theorems with the help of truth tables.
(c)
7 marks

Simplify the following Boolean expression by means of the Tabulation method. F(A,B,C,D) =∑ m(0,1,2,4,6,8,9,11,13,15)

Q.2

14 Marks
(a)
3 marks
Converts the following nos.
i)(52)10 = ( )2
ii)(436)8 = ( )16
iii)(5C7)16 = ()10
(b)
4 marks
Show that (A ⊕B ⊕C)’ = (A ⊙B ⊙C)
(c)
7 marks

Express Boolean function in Standard Form also Find the Minterms & Maxterms.

i)F(A,B,C) = AB + A’C
ii)F(A,B,C,D) = A + B
(c)
7 marks
Design a 4 bit binary to Excess-3 converter.

Q.3

14 Marks
(a)
3 marks
What is race around condition in JK flip-flop.
(b)
4 marks
Design 3-bit odd parity Generator.
(c)
7 marks

Explain SR Flip-Flop circuit using its symbol, block diagram, truth table and characteristics equation.

(a)
3 marks

Draw logic diagram, graphical symbol and Characteristic table for clocked D flip-flop.

(b)
4 marks
Compare ROM, PLA and PAL.
(c)
7 marks
Explain Master Slave JK flip-flop with truth table and circuit diagram.

Q.4

14 Marks
(a)
3 marks
Discuss general state machine architecture.
(b)
4 marks

Implement the following expression using 8:1 mux F(A,B,C,D)=∑m(0,1,3,5,7,10,11,13,14,15).

(c)
7 marks
Draw and explain Ring counter.
(a)
3 marks
Explain edge triggering and level triggering.
(b)
4 marks

Explain full adder and design a full adder circuit using 3 to 8 decoder and two OR gates.

(c)
7 marks
Design Modulo-8 counter using T flip-flop.

Q.5

14 Marks
(a)
3 marks
Give comparison of TTL and CMOS family.
(b)
4 marks
Explain different modeling styles in Verilog.
(c)
7 marks

Describe the operation of Bi-directional Shift Register with parallel load With necessary logic diagram.

(a)
3 marks
Define:
i)Power dissipation
ii)Noise Margin
iii)Figure of merit
(b)
4 marks
Explain Moore machine.
(c)
7 marks
Write a short note on FPGA.

More Digital System Design papers

Questions repeat across sessions. Working through two or three papers shows you which topics GTU asks most.

Summer 202670 marks · 5 questions
Summer 202570 marks · 5 questions
Summer 202470 marks · 5 questions

Other Semester 3 subjects

BE EC

3131101
Control Systems
3131103
Network Theory
BE03000161
Network Theory
BE03000171
Signals and Systems

Preparing with friends?

Send this paper to your class group. Every question has its own link.

About this paper

Official Gujarat Technological University (GTU) examination paper for Digital System Design (Winter 2025, B.E. · EC Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

Download official PDF All Digital System Design Papers (4) →Report a typo or correction
ViewDownload PDF