Q.1
14 Marks(a)
Convert the decimal number 250.5 to base 3, base 7 and base 8.
(b)
Show that NAND Gate is a Universal Gate.
(c)
simplify the following Boolean function, F(w,x,y,z)=∑m(2,6,8,9,10,11,14,15) using Quine-McClukey tabular Method.
Gujarat Technological UniversitySummer 2024 examination
GTU 3131102 Digital System Design Summer 2024 Question Paper & PDF
B.E. · EC Engineering · Semester 3 · Subject code 3131102
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 10:30 AM – 1:00 PM
- Questions
- 5 with internal choice
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Q.2
14 Marks(a)
Show that (A ⊕B ⊕C)’ = (A ⊙B ⊙C).
(b)
Obtain the truth table of the function: F= xy + xyʹ + yʹz.
(c)
Minimize the logic function F (A,B,C,D)= ПM(1, 2, 3, 8, 9, 10, 11,14) using K map & Draw the logic circuit for the simplified function using NOR gates only.
OR
(c)
What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer.
Q.3
14 Marks(a)
What is race around condition in JK flip flop?
(b)
List out problems of asynchronous circuit. Also exemplify any two problems with suitable examples.
(c)
With necessary sketch explain Bidirectional Shift Register with parallel load.
OR
(a)
Implement 8x1 MUX using 4x1 MUX.
(b)
Implement 4x16 decoder using two 3x8 decoder.
(c)
Explain working of master-slave JK flip-flop with necessary logic diagram, state equation and state diagram.
Q.4
14 Marks(a)
Define the terms 1. Fan out 2.Noise Margin 3. Fan in
(b)
Design Modulo-8 counter using T flip flop.
(c)
Explain Moore machine.
OR
(a)
How many flip-flops are required to build a digital counter to count from 0 to 63? Justify.
(b)
What are the classifications of Logic families? Also list the characteristics of digital IC.
(c)
Compare ROM, PLA and PAL.
Q.5
14 Marks(a)
List the steps in VLSI Design flow.
(b)
Describe General State Machine Architecture with suitable diagrams.
(c)
Design a synchronous BCD counter with JK flip-flops.
OR
(a)
Implement T flip flop using D flip flop.
(b)
Explain 4 bit serial in serial out shift register.
(c)
Design 4-bit ripple counter using negative edge triggered JK flip flop.
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About this paper
Official Gujarat Technological University (GTU) examination paper for Digital System Design (Summer 2024, B.E. · EC Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.