Q.1
14 Marks(a)
Differentiate following terms: Testing and Verification
Also asked in Summer 2026 Q1b, Summer 2025 Q1b
(c)
Explain testing methodology for transistor faults in two-input CMOS NAND Gate.
Also asked in Summer 2025 Q2c
Gujarat Technological UniversityWinter 2025 examination
GTU 3171111 Testing and Verification Winter 2025 Question Paper & PDF
B.E. · EC Engineering · Semester 7 · Subject code 3171111
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 10:30 AM – 1:00 PM
- Questions
- 5 with internal choice
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10 of 25 questions on this paper were also asked in other years. 2 more are types of question GTU sets again with new data. Each is marked below with the years it appeared.See all 15 repeated 3171111 questions, most asked first
Q.2
14 Marks(b)
Obtain Controllability and Observability for various signals of 4 inputs AND using SCOAP and Probability based testability analysis.
Also asked in Summer 2025 Q2b
(c)
Explain Muxed-D full scan design architecture in detail with necessary waveform.
OR
(c)
What is test point insertion? Explain observation point insertion.
Q.3
14 Marks(b)
List down Typical Ad hoc DFT techniques.
(c)
List down different types of Scan architectures and explain any one in brief.
OR
(b)
What is scan reordering? List and explain different types of it.
(c)
Prepare a table showing different design style with Scan design rule and recommended solution.
Also asked in Summer 2026 Q2c
Q.4
14 Marks(a)
Explain compile code simulation.
(b)
List down different alternative to fault simulation.
(c)
Describe parallel fault simulation method with example in detail.
OR
(b)
Write down importance of assertions in verification.
(c)
Explain various timing models.
Q.5
14 Marks(a)
Explain: black box verification and White box verification
(b)
Design half subtractor and write it test bench using any hardware description language
Also asked in Summer 2026 Q5c OR, Summer 2025 Q4b OR
(c)
List down different types of simulation models and explain any one of them.
OR
(a)
Discuss limitations of linting tools.
(b)
System Verilog is preferred over other hardware verification languages to implement Test Benches in industry. Why?
Also asked in Summer 2026 Q5a OR
(c)
What is code coverage? List down various types of code coverage. Explain any two in detail
Also asked in Summer 2026 Q5c, Summer 2025 Q5b
More Testing and Verification papers
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About this paper
Official Gujarat Technological University (GTU) examination paper for Testing and Verification (Winter 2025, B.E. · EC Engineering, Sem 7). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.