Q.1
14 Marks(a)
Write down challenges in VLSI Testing.
(c)
Define following terms:
1Equivalent Faults 2. Fault 3. Reject Rate 4. Rule of Ten
5Fault coverage 6. Defect level 7. Fault detection efficiency
Gujarat Technological UniversitySummer 2025 examination
GTU 3171111 Testing and Verification Summer 2025 Question Paper & PDF
B.E. · EC Engineering · Semester 7 · Subject code 3171111
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 2:30 PM – 5:00 PM
- Questions
- 5 with internal choice
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8 of 25 questions on this paper were also asked in other years. 2 more are types of question GTU sets again with new data. Each is marked below with the years it appeared.See all 15 repeated 3171111 questions, most asked first
Q.2
14 Marks(b)
Obtain Controllability and Observability for various signals of 5 inputs OR Gate using SCOAP and Probability based testability analysis.
Also asked in Winter 2025 Q2b
(c)
Explain testing methodology for transistor faults in two-input CMOS NAND Gate.
Also asked in Winter 2025 Q1c
OR
(c)
What is mean by scan design rules? Explain scan design rules for following design styles.
1Derived Clocks 2.Combinational feedback loops
Q.3
14 Marks(b)
Explain input scanning method for logic element evaluation.
(c)
Draw and explain Clocked scan cell design with the help necessary waveforms.
Also asked in Summer 2026 Q4a
OR
(a)
What are the advantages of parallel fault simulation? Name the different approaches of it.
Also asked in Summer 2026 Q4b
(b)
Explain toggle coverage and fault sampling.
(c)
Draw and explain scan design flow.
Q.4
14 Marks(a)
Explain logic optimization process for logic simulation.
(b)
Draw and explain two pass for nominal event driven strategy.
(c)
What is the need of timing models in testing? List down various time models and explain any one of them in detail.
OR
(a)
What is the importance and role of verification plan?
(b)
Write a VHDL/Verilog code and test bench for 1 X 4 demux.
Also asked in Summer 2026 Q5c OR, Winter 2025 Q5b
(c)
Draw and explain flowchart indicating steps to do concurrent fault simulation.
Also asked in Winter 2025 Q3a OR
Q.5
14 Marks(a)
What is mean by functional coverage? How it is useful in verification flow?
(b)
What is code coverage? Explain its role in verification.
Also asked in Summer 2026 Q5c, Winter 2025 Q5c OR
(c)
Compare following:
White box verification, Black box verification and Grey box verification.
OR
(a)
Differentiate between static hazard and dynamic hazard.
(b)
Compare Code driven simulation and event driven simulation
(c)
Draw and explain verification flow.
More Testing and Verification papers
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Other Semester 7 subjects
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About this paper
Official Gujarat Technological University (GTU) examination paper for Testing and Verification (Summer 2025, B.E. · EC Engineering, Sem 7). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.