What is the exam pattern and passing mark for GTU Testing and Verification (3171111)?

The GTU theory examination carries 70 total marks with a duration of 2.5 Hours. Minimum passing criteria is 23 marks (33%). The paper consists of 5 main questions with official marking breakdown and internal choices.

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Gujarat Technological UniversitySummer 2026 examination

GTU 3171111 Testing and Verification Summer 2026 Question Paper & PDF

B.E. · EC Engineering · Semester 7 · Subject code 3171111

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Total: 70 marks
To pass: 23 marks (33%)
Duration: 2.5 Hours 2:30 PM – 5:00 PM
Questions: 5 with internal choice

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10 of 25 questions on this paper were also asked in other years. 1 more is a type of question GTU sets again with new data. Each is marked below with the years it appeared.See all 15 repeated 3171111 questions, most asked first

Q.1

14 Marks

(a)

3 marks

Define following: 1.fault coverage 2.yield 3. fault detection efficiency.

(b)

4 marksAsked in 3 of 3 papers

Explain the difference between testing and verification in the VLSI life cycle.

Also asked in Winter 2025 Q1a, Summer 2025 Q1b

(c)

7 marksAsked in 2 of 3 papers

What is the use of bridging fault models in VLSI Testing?List down and explain various bridging fault models.

Also asked in Summer 2025 Q2a

Q.2

14 Marks

(a)

3 marks

Differentiate between Ad hoc DFT techniques and Structured DFT.

(b)

4 marksAsked in 2 of 3 papers

What are the different levels of abstraction in VLSI testing?Explain if brief.

Also asked in Winter 2025 Q2a

(c)

7 marksAsked in 2 of 3 papers

What is mean by scan design rules? Prepare a table showing design style, its scan design rule and recommended solution for it.

Also asked in Winter 2025 Q3c OR

(c)

7 marks

Demonstrate how a set of three D flip-flops can be converted into a scan chain using Muxed D design.

Q.3

14 Marks

(a)

3 marks

Draw and explain RTL testability repair design flow.

(b)

4 marks

Compare: Fault simulation and Logic simulation

(c)

7 marksAsked in 2 of 3 papers

Explain the purpose of scan configuration in scan synthesis with suitable examples.

Also asked in Winter 2025 Q3a

(a)

3 marks

Define Static Hazard.List and explain different types of it.

(b)

4 marks

How the signaling will be provided in scan chain in which a negative edge scan cell is followed by a positive scan cell?

(c)

7 marks

Give comparison of fault simulation techniques.

Q.4

14 Marks

(a)

3 marksAsked in 2 of 3 papers

Draw and explain clocked scan cell design with the help necessary waveforms.

Also asked in Summer 2025 Q3c

(b)

4 marksAsked in 2 of 3 papers

What are the advantages of parallel fault simulation? Name the different approaches of it

Also asked in Summer 2025 Q3a OR

(c)

7 marks

What is event driven simulation? Explain zero-event driven simulation with the help of example. Draw necessary flow chart for the same.

(a)

3 marks

Discuss wire delay.

(b)

4 marksAsked in 2 of 3 papers

What is reconvergence model in verification?

Also asked in Winter 2025 Q4a OR

(c)

7 marks

What is ternary logic? Write down basic operations for ternary logic for AND, OR and NOT gate.

Q.5

14 Marks

(a)

3 marks

Write down different approaches of functional verification and define all.

(b)

4 marks

What is a verification plan? List down its components.

(c)

7 marksAsked in 3 of 3 papers

What is the role of code coverage in verification? Explain it in detail.

Also asked in Winter 2025 Q5c OR, Summer 2025 Q5b

(a)

3 marksAsked in 2 of 3 papers

System Verilog is preferred over other hardware verification languages to implement Test Benches in industry. Why?

Also asked in Winter 2025 Q5b OR

(b)

4 marks

What is the use of linting tools ?What are the limitations of it ?

(c)

7 marksSame type asked in 3 of 3 papers

Design 1x4 demultiplexer and write its testbench in any hardware description language (HDL)

Also asked in Winter 2025 Q5b, Summer 2025 Q4b OR

More Testing and Verification papers

Questions repeat across sessions. Working through two or three papers shows you which topics GTU asks most.

Winter 202570 marks · 5 questions

Summer 202570 marks · 5 questions

Other Semester 7 subjects

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3171104

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3171105

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3171106

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3171108

Internet of Things

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About this paper

Official Gujarat Technological University (GTU) examination paper for Testing and Verification (Summer 2026, B.E. · EC Engineering, Sem 7). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

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