Gujarat Technological UniversityWinter 2025 examination

GTU 3151105 VLSI Design Winter 2025 Question Paper & PDF

B.E. · EC Engineering · Semester 5 · Subject code 3151105
Download official PDFView PDF here
Share with your class
Total
70 marks
To pass
23 marks (33%)
Duration
2.5 Hours 10:30 AM – 1:00 PM
Questions
5 with internal choice
No solutions on this paper yetNeed them for your exam? Ask once. Papers that students ask for are solved first, and we aim to add them within 24 hours.

Q.1

14 Marks
(a)
3 marks
What is chip reliability? List the four major causes of chip reliability issues.
(b)
4 marks

Explain the channel length modulation effect in n-channel MOSFET operation.

(c)
7 marks

Explain the MOS system under external bias for accumulation and depletion region. region.

Q.2

14 Marks
(a)
3 marks
What is substrate bias effect?
(b)
4 marks

Compare and explain the full custom and semi-custom design style of VLSI.

(c)
7 marks

Draw and explain the basic steps of Local oxidation of Silicon (LOCOS) process.

(c)
7 marks
Explain the process steps for fabrication of n-channel MOSFET.

Q.3

14 Marks
(a)
3 marks
Explain RC delay models for calculation of interconnect delay.
(b)
4 marks
For depletion load n MOS inverter circuit, derive the equation of VIL.
(c)
7 marks

Consider the CMOS inverter circuit with following parameters: VDD = 3.3V, kn =200 μA/V², kp =80 μA/V², VTO,n = 0.6V, VTO,p = -0.7V. Calculate the VIL and VOH on the VTC of the inverter.

(a)
3 marks

Draw the circuit of 2 input CMOS NAND gate and explain its working with the help of truth table.

(b)
4 marks

Why in symmetrical and ideal CMOS inverter required (W/L)p ≈ 2.5 (W/L)n ? Explain in detail.

(c)
7 marks

Consider a resistive load inverter circuit with VDD= 5V, k’n =20μA/V², VTO = 0.8V, RL = 200 kΩ and W/L =2. Calculate VOL and VIH on the VTC of the inverter.

Q.4

14 Marks
(a)
3 marks

Explain AOI (AND-OR-INVERT) and OAI (OR-AND-INVERT) circuit categories with example for CMOS logic.

(b)
4 marks
Derive switching power dissipation equation of CMOS inverter.
(c)
7 marks

How logic “1” transfer happens in nMOS pass transistor circuits. Explain with suitable example.

(a)
3 marks

Draw the AOI based implementation of the clocked NOR based SR latch circuit.

(b)
4 marks
Implement XOR function using CMOS TG (Transmission Gates).
(c)
7 marks

Explain various on chip clock generation circuits and distribution networks.

Q.5

14 Marks
(a)
3 marks
Draw the CMOS implementation of D-latch.
(b)
4 marks
What is controllability and observability for design for testability (DFT)?
(c)
7 marks

How pre-charge and evaluate logic works for dynamic CMOS circuit? Explain with example.

(a)
3 marks
Compare FinFET and Planner MOSFET.
(b)
4 marks
Explain scan-based techniques for DFT with one example.
(c)
7 marks

Define propagation delay τPHL and obtain its expression for CMOS inverter circuit.

More VLSI Design papers

Questions repeat across sessions. Working through two or three papers shows you which topics GTU asks most.

Summer 202670 marks · 5 questions
Summer 202570 marks · 5 questions

Other Semester 5 subjects

BE EC

2151101
Audio Video Systems
3151103
Principles of Management
3151104
Analog and Digital Communication
3151106
Power Electronics

Preparing with friends?

Send this paper to your class group. Every question has its own link.

About this paper

Official Gujarat Technological University (GTU) examination paper for VLSI Design (Winter 2025, B.E. · EC Engineering, Sem 5). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

Download official PDF All VLSI Design Papers (3) →Report a typo or correction
ViewDownload PDF