Q.1
14 Marks(a)
Present device isolation techniques in fabrication process.
(b)
Explain the MOS system under external bias.
(c)
Describe the working of edge-triggered flip-flops with necessary diagrams.
Gujarat Technological UniversitySummer 2025 examination
GTU 3151105 VLSI Design Summer 2025 Question Paper & PDF
B.E. · EC Engineering · Semester 5 · Subject code 3151105
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 2:30 PM – 5:00 PM
- Questions
- 5 with internal choice
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Q.2
14 Marks(a)
Explain the basic principles of pass transistor circuits.
(b)
Design 2-input OR, AND and XOR gate using CMOS.
(c)
Present the analysis of the resistive load inverter. Derive critical voltages and noise margins.
OR
(c)
Analyze transmission gates (TGs) in detail. Also, describe the procedure for circuit design with TGs.
Q.3
14 Marks(a)
Enlist MOSFET scaling and small-geometry effects.
(b)
Discuss synchronous dynamic circuit techniques.
(c)
Present timing analysis of CMOS inverter.
OR
(a)
What is the built-in self-test (BIST)? Explain this technique in brief.
(b)
Describe the behavior of bistable elements.
(c)
Explain voltage bootstrapping.
Q.4
14 Marks(a)
Write the equations describing the current-voltage characteristics of MOSFET.
(b)
Describe fabrication of nMOS Transistor.
(c)
Analyze the factors behind latch-up problems. Also, explain the techniques for its prevention.
OR
(a)
What is the substrate bias effect? Explain its analysis.
(b)
Discuss switching power dissipation of CMOS inverters.
(c)
Present the analysis of on-chip clock generation and distribution techniques.
Q.5
14 Marks(a)
Define and explain DIBL.
(b)
Present delay-time definitions.
(c)
Discuss fault types and models.
OR
(a)
Explain controllability and observability.
(b)
Describe the operating principle of the SR latch circuit with the necessary diagrams.
(c)
What are the needs of FinFET devices? Explain FinFET devices in detail. Also, compare them with planar MOSFET.
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About this paper
Official Gujarat Technological University (GTU) examination paper for VLSI Design (Summer 2025, B.E. · EC Engineering, Sem 5). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.