Q.1
14 Marks(a)
Draw VLSI Design Flow y chart and flow chart.
(b)
Define Regularity, Modularity and Locality
(c)
Derive threshold voltage equation of MOSFET
Gujarat Technological UniversitySummer 2026 examination
GTU 3151105 VLSI Design Summer 2026 Question Paper & PDF
B.E. · EC Engineering · Semester 5 · Subject code 3151105
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 2:30 PM – 5:00 PM
- Questions
- 5 with internal choice
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Q.2
14 Marks(a)
Compare Full custom, Semi-custom and Fully Programmable VLSI design style.
(b)
Compare Constant field and constant voltage Scaling techniques of MOSFET.
(c)
Explain Fabrication of n-MOSFET with neat sketch.
OR
(c)
Derive drain current using gradual channel approximate
Q.3
14 Marks(a)
Draw VTC of practical Inverter and define all critical voltages
(b)
Draw resistive load inverter and Derive VIH critical voltage equation of it.
(c)
Consider a resistive-load inverter circuit with VDD=5V, kn'= 20 uA/V2, VT0= 0.8 V, RL = 200 kΩ, and W/L = 2. Find noise margin high MNH.
OR
(a)
What is need of Design of Testability and Define Controllability and observability
(b)
Draw CMOS inverter and Derive VIL critical voltage equation of it.
(c)
Consider a CMOS inverter with the following parameters: VTon = 0.6 V, VTop = - 0.7 V, Kn = 200 uA/V2, Kp = 80 uA/V2 and VDD = 3.3 V. Find noise margin low NML.
Q.4
14 Marks(a)
Draw three stage ring oscillator circuit and derive it generated signal frequency equation
(b)
Realize the following Boolean function using Transmission Gate: F=AB+A’C’+AB’C
(c)
Draw i/p and o/p waveform during high to low transition of o/p for CMOS inverter and derive expression for ζPHL. Using differential equation method
OR
(a)
Draw the circuit diagram of domino CMOS logic gate
(b)
Draw CMOS implementation of D latch with two inverters and two CMOS TG gates.
(c)
Derive switching power dissipation equation of CMOS inverter with idea step input.
Q.5
14 Marks(a)
Compare FinFET and Planar MOSFET
(b)
What is the need of voltage bootstrapping? Draw voltage bootstrapping circuit.
(c)
What is clock skew. Draw and Explain on chip clock generation and distribution circuits.
OR
(a)
Implement clocked JK latch using CMOS inverter.
(b)
Explain latch up problem in CMOS inverter. Mention causes and remedy for avoiding latch up.
(c)
Write a short note on Built In Self Test(BIST).
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About this paper
Official Gujarat Technological University (GTU) examination paper for VLSI Design (Summer 2026, B.E. · EC Engineering, Sem 5). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.