GTU BE03009011 Analog and Digital Electronics Winter 2025 Solved Paper & Solutions

The symbols below are the IEC (rectangular) symbols. The small circle at the output means NOT.

NAND is $Y = \overline{A\cdot B}$, NOR is $Y = \overline{A + B}$, and EX-NOR is $Y = \overline{A \oplus B}$. The EX-NOR output is 1 when the two inputs are equal.

1. Slew rate: the maximum rate of change of the output voltage with time, $SR = \left.\dfrac{dV_o}{dt}\right|_{max}$. It is in V/$\mu$s (0.5 V/$\mu$s for the 741). It limits how fast the output can follow a large, fast input.
2. CMRR (common mode rejection ratio): the ratio of the differential gain to the common mode gain, $CMRR = \dfrac{A_d}{A_{cm}}$, often in dB. It shows how well the op-amp rejects noise common to both inputs. The ideal value is infinite (about 90 dB for the 741).
3. Output offset voltage: the DC voltage at the output when both inputs are grounded. It is ideally zero, and it is caused by the input offset voltage and the bias currents.
4. Input bias current: the average of the two input currents, $I_B = \dfrac{I_{B1} + I_{B2}}{2}$, needed to bias the input transistors. It is about 80 nA for the 741.

An op-amp is a direct coupled, high gain amplifier. It is made of four blocks one after the other.

1. Input stage (dual input, balanced output differential amplifier): it amplifies the difference of the two input signals and rejects the common signal. It gives the op-amp its high input resistance and its high CMRR, and it decides the input offset and bias currents.
2. Intermediate stage (dual input, unbalanced output differential amplifier): it takes the balanced output of the first stage and gives a single ended output. It gives most of the voltage gain.
3. Level shifter: the stages are direct coupled, so the DC level rises stage by stage. The level shifter (an emitter follower with a current source) brings the DC level down to zero when the input is zero, so that the output can swing both positive and negative.
4. Output stage (push-pull complementary emitter follower): it gives a low output resistance, so that the op-amp can drive a load. It also gives a large output voltage swing, and it protects against a short circuit.

The gain of the whole op-amp is the product of the gains of the stages, and it is very high (about 200000 for the 741). Negative feedback is then used to fix the gain at a lower, stable value.

• Inverting amplifier: the input is applied to the inverting (−) terminal, and the non-inverting terminal is grounded. The output is 180 degrees out of phase with the input. The gain is $A_F = -\dfrac{R_F}{R_1}$.
• Non-inverting amplifier: the input is applied to the non-inverting (+) terminal. The output is in phase with the input. The gain is $A_F = 1 + \dfrac{R_F}{R_1}$.
• Differential amplifier: the two inputs $V_1$ and $V_2$ are applied at the two terminals, and the output is proportional to their difference, $V_o = \dfrac{R_F}{R_1}(V_2 - V_1)$.

A zero crossing detector is a comparator whose reference voltage is zero. It tells when the input signal crosses zero volts.

Working: when $V_{in} > 0$, the output goes to the positive saturation voltage $+V_{sat}$. When $V_{in} < 0$, the output goes to $-V_{sat}$. Each time the input passes through zero, the output changes its state. If the input is a sine wave, the output is a square wave of the same frequency.

The input is applied to the other terminal for an inverting zero crossing detector, and the output is then inverted. Uses: a square wave from a sine wave, a phase detector, and a frequency counter.

Given: $A = 200000$, $R_i = 2\ \text{M}\Omega$, $R_o = 75\ \Omega$, $f_o = 5$ Hz. The circuit is a non-inverting amplifier with $R_1 = 1\ \text{k}\Omega$ and $R_F = 10\ \text{k}\Omega$.

Notice that the closed loop gain is small (11), but the input resistance is very large and the output resistance is very small, so the amplifier is close to an ideal one. The output swing is limited to $\pm 13$ V.

Check: the gain bandwidth product is $A_F\times f_F = 11 \times 90.9\ \text{kHz} = 1$ MHz, which equals $A\times f_o = 200000 \times 5 = 1$ MHz.

A triangular wave generator uses two op-amps. A1 is a comparator with positive feedback (a Schmitt trigger) and gives a square wave. A2 is an integrator and changes it to a triangular wave.

When $V_1$ is high, the integrator output ramps down, and when it is low the output ramps up. When the ramp reaches the threshold of A1, set by $R_2$ and $R_3$, the comparator changes state, and the ramp reverses. The frequency is set by $R$, $C$, $R_2$ and $R_3$.

A comparator compares the input voltage with a reference voltage $V_{ref}$, and the output is at one of two levels, $+V_{sat}$ or $-V_{sat}$.

For a non-inverting comparator, with the input at the + terminal and $V_{ref}$ at the − terminal:

• When $V_{in} > V_{ref}$, the output is $+V_{sat}$.
• When $V_{in} < V_{ref}$, the output is $-V_{sat}$.

The transition is very sharp, as the open loop gain is very high, so a small difference decides the output. For an inverting comparator the transfer characteristic is the mirror image. Uses: a zero crossing detector, a level detector and an analogue to digital converter. Its drawback is that noise near $V_{ref}$ causes false switching, and this is removed with a Schmitt trigger.

The LM317 is a three terminal adjustable positive voltage regulator. Its output can be set from 1.25 V to 37 V at up to 1.5 A. The terminals are input (IN), output (OUT) and adjust (ADJ).

Working: the regulator keeps a fixed reference voltage of 1.25 V between the OUT and ADJ terminals. That is across the resistor $R_1$, so the current in $R_1$ is $\dfrac{1.25}{R_1}$, which is fixed. This same current flows in $R_2$ too (adding the very small ADJ current $I_{adj}$, about 50 $\mu$A). The output voltage is the sum of the 1.25 V and the drop in $R_2$:

The second term is small, so $V_o \approx 1.25\left(1 + \dfrac{R_2}{R_1}\right)$. By changing the pot $R_2$, the output voltage changes. The usual value is $R_1 = 240\ \Omega$.

Example: $R_1 = 240\ \Omega$ and $R_2 = 2.4\ \text{k}\Omega$ give $V_o = 1.25\times(1 + 10) = 13.75$ V.

If the input rises or the load changes, the internal error amplifier keeps the 1.25 V reference, so $V_o$ stays constant. The input voltage must be at least 3 V higher than the output (the dropout). So for a 13.75 V output the input must be about 17 V or more. The regulator also gives good line regulation and load regulation, which means that the output changes very little when the input or the load changes. The input capacitor $C_1$ removes the line noise, and $C_2$ improves the ripple rejection. The IC has thermal shutdown and current limiting, so it is protected from overload and a short circuit.

Both have the same function, but the input levels are opposite.

Classification of registers

A. Based on data shifting (the way data goes in and out):

1. Serial in serial out (SISO): data enters and leaves one bit at a time.
2. Serial in parallel out (SIPO): data enters serially, and all bits are read at once.
3. Parallel in serial out (PISO): all bits are loaded at once, and read one at a time.
4. Parallel in parallel out (PIPO): all bits are loaded and read at once.

By the direction of the shift, a register may be a shift right, a shift left, or a bidirectional register.

B. Based on circuit technology:

1. Bipolar registers use transistors in TTL or ECL. They are fast, but they use more power.
2. MOS registers use NMOS or CMOS. They use less power and give high packing density.

Registers are also called static (the data is kept as long as the power is on) or dynamic (the data is kept as charge on the gate capacitance and must be refreshed). Flip-flops are the basic element of the static register.

A decade (MOD-10) counter counts from 0 to 9 (0000 to 1001) and then returns to 0. It needs 4 flip-flops, as $2^3 < 10 \le 2^4$. A 4-bit binary counter counts to 15, so it is reset at the count 10 (1010).

Logic diagram (asynchronous / ripple type): four JK flip-flops, all with $J = K = 1$ (toggle). The clock goes to FF-A, and each other flip-flop is clocked by the output of the one before it. The outputs $Q_B$ and $Q_D$ go to a NAND gate, and its output is joined to the clear inputs.

Working:

1. Counting goes in the binary way, 0000, 0001, ..., 1001 (9).
2. On the 10th clock pulse the count becomes 1010. Then $Q_B = 1$ and $Q_D = 1$, so the NAND output goes low, and all flip-flops are cleared at once. The count returns to 0000.
3. The state 1010 lasts only for a very short time (a few nanoseconds), so it is not seen in the output.

Timing diagram (negative edge triggered):

$Q_A$ has half the clock frequency, and $Q_D$ has $\tfrac{1}{10}$ of it. So the counter is also a divide by 10 circuit.

Applications of a digital to analog converter (DAC):

1. Digital audio: in CD players, phones and sound cards, to change the stored digital sound into an analogue signal for the speaker.
2. Digital control systems: the digital output of a computer drives the analogue motors and valves.
3. Waveform and function generators, where the samples are stored in memory.
4. Video displays, digitally controlled amplifiers and attenuators, and modems.
5. It is also a part of some analog to digital converters (counter and successive approximation types).

A 2-bit digital comparator compares two 2-bit numbers $A = A_1A_0$ and $B = B_1B_0$. It has three outputs: $A > B$, $A = B$ and $A < B$. Only one of them is 1.

Truth table:

Equations: let $x_i = A_i \odot B_i$ (1 when the two bits are equal).

Logic diagram:

The first bit decides the result if the MSBs differ. If they are equal, the LSBs decide.

In a voltage to time conversion ADC (the single slope or ramp type), the input voltage is first changed into a time interval, and the time is measured by counting clock pulses.

Working:

1. The start signal resets the counter to zero and starts the ramp generator (an integrator with a constant input). The ramp rises linearly, $V_{ramp} = kt$.
2. The comparator output is high as long as $V_{ramp} < V_{in}$. This opens the AND gate, and the clock pulses go to the counter.
3. When $V_{ramp}$ becomes equal to $V_{in}$, the comparator output goes low, the gate closes and the counter stops.
4. The time is $t = \dfrac{V_{in}}{k}$, so the count is proportional to the input voltage:

Waveforms:

Example: the ramp is 1 V/ms, the clock is 1 MHz and $V_{in} = 2.5$ V. Then $t = 2.5$ ms and $N = 2500$ counts. Each count is 1 mV.

The conversion time is not fixed. It is longest when $V_{in}$ is at full scale, and it is $\dfrac{V_{FS}}{k}$. After each conversion the ramp is reset and the counter is cleared. The counter output is the digital value, and it may be latched for display.

Drawback: the accuracy depends on the ramp slope and the clock frequency, which drift with temperature. The dual slope ADC removes this problem, but it is slower.