Gujarat Technological UniversitySummer 2025 examination

GTU 2161101 VLSI Technology & Design Summer 2025 Question Paper & PDF

B.E. · EC Engineering · Semester 6 · Subject code 2161101
Download official PDFView PDF here
Share with your class
Total
70 marks
To pass
23 marks (33%)
Duration
2.5 Hours 10:30 AM – 1:00 PM
Questions
5 with internal choice
No solutions on this paper yetNeed them for your exam? Ask once. Papers that students ask for are solved first, and we aim to add them within 24 hours.

Q.1

14 Marks
(a)
7 marks
Provide a comparative analysis of Semi-custom and Full-custom VLSI design styles.
(b)
7 marks

Explain the behaviour of MOS device under external bias with the help of energy band diagrams and derive the relationship for maximum depletion width at oxide- semiconductor surface.

Q.2

14 Marks
(a)
7 marks

Explain LOCOS technique used for device isolation and state its advantages over the Etched Field Oxidation technique.

(b)
7 marks
Explain the experimental methods of measuring following parameters of nMOS:

Threshold voltage (VT), channel length modulation coefficient (λ), substrate-bias coefficient (γ), transconductance parameter (kn)

(b)
7 marks
Consider a MOS system with the following parameters:

tox = 20 nm ΦGC = -0.85 V NA = 2 x 10⁵ cm-3 Qox = q x 2 x 10¹¹ C/cm²

i)Determine the threshold voltage, VT0 under zero bias at room temperature (T = 300 °K). Consider εox = 3.97ε0 and εSi = 11.7ε0
ii)Determine the type (p-type or n-type) and amount of channel implant (NI /cm²) required to change the threshold voltage to 0.8 V.

Q.3

14 Marks
(a)
7 marks
Explain resistive load inverter in detail with necessary derivations of VOL, VOH, VIL, VIH.
(b)
7 marks
Explain the MOSFET capacitances in detail.
(a)
7 marks
Describe Elmore Delay technique to estimate the delay of interconnects.
(b)
7 marks

Explain the latch-up problem observed in CMOS circuits and mention various techniques to prevent it.

Q.4

14 Marks
(a)
7 marks

Draw two-input CMOS NOR and NAND gate circuits. Identify the transistor/s suffering from body bias effect in each of these circuits. Assume single-well CMOS technology

(b)
7 marks
Draw the circuit diagram of a CMOS edge-triggered D-flip-flop and explain.
(a)
7 marks
Discuss the on-chip clock generation and distribution.
(b)
7 marks
Explain the Domino CMOS dynamic logic circuit design in detail.

Q.5

14 Marks
(a)
7 marks

Explain the basic principles of pass transistor circuits. Also explain logic “0” and logic “1” transfer.

(b)
7 marks
Explain the Built-In-Self-Test (BIST) technique for testing VLSI designs.
(a)
7 marks

What is the need of voltage bootstrapping? Draw MOSFET based voltage bootstrapping circuit and explain it in detail with mathematical derivations.

(b)
7 marks
Write a short note on CMOS Transmission gate.

More VLSI Technology & Design papers

Questions repeat across sessions. Working through two or three papers shows you which topics GTU asks most.

Summer 202470 marks · 5 questions

Other Semester 6 subjects

BE EC

2161102
Advanced Microprocessor
2161103
Telecommunication Switching systems and Networks

Preparing with friends?

Send this paper to your class group. Every question has its own link.

About this paper

Official Gujarat Technological University (GTU) examination paper for VLSI Technology & Design (Summer 2025, B.E. · EC Engineering, Sem 6). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.

Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.

Download official PDF All VLSI Technology & Design Papers (2) →Report a typo or correction
ViewDownload PDF