Q.1
14 Marks(a)
Compare Semi-custom and Full custom VLSI design style
(b)
Discuss VLSI design flow in brief
(c)
Compare constant electric field scaling and constant voltage scaling in detail.
Gujarat Technological UniversitySummer 2024 examination
GTU 2161101 VLSI Technology & Design Summer 2024 Question Paper & PDF
B.E. · EC Engineering · Semester 6 · Subject code 2161101
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 10:30 AM – 1:00 PM
- Questions
- 5 with internal choice
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Q.2
14 Marks(a)
Explain LOCOS method in detail.
(b)
Explain the concept of regularity and modularity in brief.
(c)
Explain MOSFET capacitances in detail.
OR
(c)
Discuss fabrication process of n-channel MOSFET in detail.
Q.3
14 Marks(a)
Draw and explain I-V characteristic of nMOS transistor.
(b)
Explain the channel length modulation effect in detail.
(c)
Explain MOS system under external bias in detail with suitable energy-band diagrams.
OR
(a)
Explain FPGA in brief.
(b)
Draw and explain the CMOS inverter circuit
(c)
Draw circuit of nMOS resistive load inverter. Derive VIH , VIL ,VOL and VOH for the same.
Q.4
14 Marks(a)
What is CMOS ring oscillator? Explain in brief.
(b)
Explain behavior of bi-stable element in brief.
(c)
Define the propagation delay τPHL and τPLH Derive τPHL for CMOS inverter.
OR
(a)
Prove that switching power dissipation of CMOS inverter is proportional to switching frequency.
(b)
Explain Generalized NOR structure with Multiple inputs using combinational MOS logic circuits.
(c)
Derive the threshold voltage expression for CMOS two input NAND Gate.
Q.5
14 Marks(a)
Explain controllability and observabality in brief.
(b)
Explain Adhoc testable design technique in brief.
(c)
Explain voltage Bootstrapping in detail.
OR
(a)
Explain Latch-up prevention technique.
(b)
Write short note on Complimentary pass transistor logic (CPL)
(c)
Explain Dynamic CMOS Logic (Precharge-Evaluate Logic) in detail. Also illustrate the cascading problem in dynamic CMOS logic.
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About this paper
Official Gujarat Technological University (GTU) examination paper for VLSI Technology & Design (Summer 2024, B.E. · EC Engineering, Sem 6). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.