GTU 3110016 Basic Electronics (BE) Winter 2024 Solved Paper & Solutions

Ideal Diode vs. Practical Diode Characteristics

1. Ideal Diode:

• Forward Bias ($V \ge 0$): Acts as an ideal short circuit (zero internal resistance, zero threshold drop, $V_D = 0\text{ V}$).
• Reverse Bias ($V < 0$): Acts as an ideal open circuit (infinite resistance, zero reverse leakage current, $I = 0\text{ A}$).

2. Practical Diode (Silicon):

• Cut-in / Knee Voltage ($V_\gamma$): Requires approximately $0.7\text{ V}$ (Silicon) or $0.3\text{ V}$ (Germanium) to overcome the depletion barrier before conducting significant forward current.
• Reverse Saturation Current ($I_0$): A minute leakage current (in nanoamperes for Si) flows due to minority charge carriers until reaching the reverse breakdown voltage ($V_{BR}$).

Center-Tapped Two-Diode Full-Wave Rectifier

Operation

1. Positive Half-Cycle:

• Anode of $D_1$ is positive; Anode of $D_2$ is negative with respect to center-tap.
• $D_1$ is forward-biased (ON) and $D_2$ is reverse-biased (OFF). Current flows from $D_1$ through load resistor $R_L$ to center-tap.

2. Negative Half-Cycle:

• Anode of $D_1$ becomes negative; Anode of $D_2$ becomes positive with respect to center-tap.
• $D_1$ is OFF and $D_2$ is forward-biased (ON). Current again flows through $R_L$ in the identical direction.

3. Key Specifications:

• Peak Inverse Voltage (PIV): $2V_m$
• Rectification Efficiency: $\eta = 81.2\%$
• Ripple Frequency: $2f_{in} = 100\text{ Hz}$

Voltage Clamper Circuits

A clamper circuit shifts an alternating input waveform to a different DC level without altering the peak-to-peak amplitude or shape of the applied signal.

1. Positive Clamper Circuit

Shifts the entire input signal upward such that the negative peaks clamp to the $0\text{ V}$ reference line.

• Working:
• During the negative half-cycle ($-V_m$), the diode is forward-biased (short circuit). Capacitor $C$ charges rapidly to peak value $+V_m$ with polarity (+ on right, - on left).
• During the positive half-cycle ($+V_m$), the diode turns OFF. The output voltage by KVL is:

• The waveform shifts entirely into the positive region with peak-to-peak amplitude $2V_m$.

2. Negative Clamper Circuit

Shifts the entire input waveform downward such that the positive peaks clamp to the $0\text{ V}$ axis.

• Working:
• During the positive half-cycle ($+V_m$), the reversed diode conducts, charging capacitor $C$ to peak input voltage $V_m$ (+ on left, - on right).
• In the subsequent cycle, the diode remains reverse-biased:

• The output swings from $0\text{ V}$ to $-2V_m$, clamping the positive peaks to $0\text{ V}$.

Three Operating Modes of a Bipolar Junction Transistor (BJT)

(Note: An inverted mode where EBJ is reverse-biased and CBJ is forward-biased yields very low gain and is rarely utilized).

What is Transistor Biasing?

Transistor biasing is the application of appropriate external DC voltages and resistances to establish fixed, stable DC currents ($I_B, I_C$) and voltages ($V_{BE}, V_{CE}$) known as the Operating Point (Q-point).

Why Biasing is Essential

1. Maintain Active Region Operation: Ensures the EB junction remains forward-biased and the CB junction remains reverse-biased across the entire AC signal swing.
2. Prevent Signal Distortion / Clipping: Places the Q-point at the center of the DC load line to avoid premature clipping in cut-off or saturation.
3. Thermal Stability: Prevents thermal runaway caused by the temperature sensitivity of reverse saturation current ($I_{CBO}$), base-emitter voltage ($V_{BE}$), and current gain ($\beta$).

Comparison of BJT Configurations (CB, CE, and CC)

Photo-Diode Working Principle

A Photo-diode is a semiconductor p-n junction device designed to operate in reverse bias where incident light photons generate electron-hole pairs.

1. Operation: When optical light with photon energy $h\nu \ge E_g$ (bandgap energy) strikes the reverse-biased depletion region, covalent bonds break, generating new electron-hole pairs.
2. Reverse Photocurrent: The internal electric field sweeps electrons toward the n-side and holes toward the p-side, producing a reverse photocurrent ($I_\lambda$) directly proportional to light illuminance ($E$ in lux):

3. Application: Optical fiber receivers, barcode scanners, solar sensors, light meters.

Varactor Diode (Varicap)

A Varactor Diode is a specialized p-n junction diode designed to exploit the voltage-dependent junction capacitance when operated exclusively under reverse bias.

How It Works

• The depletion layer acts as a dielectric insulator sandwiched between conductive p and n regions (analogous to parallel capacitor plates):

• As reverse bias voltage ($V_R$) increases, the depletion layer width ($W$) widens:

where $n = 0.5$ for abrupt junctions.

• Increasing reverse voltage reduces junction capacitance smoothly and continuously.
• Application: Electronic tuning in FM receivers, Voltage Controlled Oscillators (VCOs), Phase-Locked Loops (PLLs).

Step 1: Identify Given Parameters

• $h_{ie} = 2.1\text{ k}\Omega = 2100\,\Omega$
• $h_{fe} = 75$
• $h_{oe} = 1\,\mu\text{S} = 1 \times 10^{-6}\text{ S}$
• Biasing resistors: $R_1 = 40\text{ k}\Omega$, $R_2 = 5\text{ k}\Omega$
• Circuit loads: $R_C = 2.2\text{ k}\Omega$, $R_L = 10\text{ k}\Omega$, $R_E = 1\text{ k}\Omega$

For a standard CE amplifier with $R_E$ bypassed by $C_E$ at AC signal frequencies:

Step 2: Calculate Equivalent AC Load Resistance ($r_L$)

Step 3: Current Gain of Transistor ($A_i$) and Amplifier ($A_{is}$)

Transistor current gain:

Step 4: Input Impedance ($Z_i$)

Input impedance looking into the base:

Equivalent base bias resistance $R_B$:

Total amplifier input impedance $Z_i$:

Step 5: Voltage Gain ($A_v$)

(The negative sign indicates a $180^\circ$ phase inversion between input and output).

Step 6: Output Impedance ($Z_o$)

Transistor output admittance looking into the collector (assuming ideal source $R_s = 0$):

Total amplifier output impedance with collector resistor $R_C$:

Key JFET Parameters

1. Saturation Drain Current ($I_{DSS}$): The maximum drain current flowing through the channel when gate-to-source voltage $V_{GS} = 0\text{ V}$ and drain-to-source voltage $V_{DS} \ge |V_P|$ (pinch-off region).
2. Pinch-Off Voltage ($V_P$ or $V_{GS(off)}$): The gate-to-source voltage at which the two opposing depletion layers touch, completely pinching off the conductive channel ($I_D = 0$).
3. Transconductance ($g_m$): The ratio of change in drain current to the change in gate-to-source voltage at constant $V_{DS}$:

Common Base (CB) Amplifier Analysis

Small-Signal AC Analysis (Using $r_e$ Model)

1. Input Impedance ($Z_i$):

Looking into the emitter terminal with base grounded:

Since $r_e = \frac{V_T}{I_E} \approx 25\,\Omega$ is very small, $Z_i \approx r_e$ (typically $20\text{--}50\,\Omega$).

2. Output Impedance ($Z_o$):

Looking into the collector terminal with input shorted ($v_i = 0$):

3. Voltage Gain ($A_v$):

Since $A_v > 0$, the voltage gain is high and non-inverting ($0^\circ$ phase shift).

Logic Gates & Basic Rules

A logic gate is an idealized electronic circuit implementing a Boolean algebraic function, producing a binary output ($0$ or $1$) based on binary inputs.

1. OR Gate Rule ($Y = A + B$):

• The output is HIGH (1) if at least one input is HIGH. The output is LOW (0) only when all inputs are LOW ($0+0=0, 0+1=1, 1+0=1, 1+1=1$).

2. AND Gate Rule ($Y = A \cdot B$):

• The output is HIGH (1) only if all inputs are HIGH. The output is LOW (0) if any input is LOW ($0\cdot0=0, 0\cdot1=0, 1\cdot0=0, 1\cdot1=1$).

Why NAND and NOR Gates are Universal Gates

NAND and NOR gates are termed universal gates because any arbitrary Boolean expression and any elementary logic gate (NOT, AND, OR, XOR, XNOR) can be implemented exclusively using combinations of either NAND gates alone or NOR gates alone without any other gate types.

Truth Table of 2-Input NAND Gate ($Y = \overline{A \cdot B}$)

Applications of Field Effect Transistor (FET)

1. FET as an Amplifier (Linear Region / Saturation)

• Principle: Biased in the saturation / pinch-off region ($V_{DS} \ge V_{GS} - V_P$). Small AC variations in gate-to-source voltage ($v_{gs}$) produce proportional changes in drain current:

• When current flows through drain resistor $R_D$, an amplified voltage appears at the output:

• Advantage: Enormous input impedance draws practically zero current from delicate sensor sources.

2. FET as a Switch (Digital Inverter / Pass Transistor)

• Principle: Operates alternately between the Cut-off Region and the Ohmic / Triode Region.
• OFF State (Cut-off): When $V_{GS} \le V_{GS(off)}$, the channel is completely pinched off ($I_D = 0$). The FET acts as an open circuit; output $V_{DS} \approx V_{DD}$.
• ON State (Ohmic): When $V_{GS} = 0\text{ V}$ (or $V_{GS} \gg V_{th}$ for MOSFET), the channel resistance $r_{DS(on)}$ drops to a few ohms. A large current flows and $V_{DS} \approx 0\text{ V}$.
• Advantage: Negligible gate drive power and absence of minority carrier storage delays allow ultra-fast nanosecond switching.