Q.1
14 Marks(a)
Define: Propagation Delay, fan-out, Noise Margin
(b)
Convert (975)11 to decimal, binary, octal and hexadecimal number.
(c)
Design a BCD to Excess-3 code converter.
Gujarat Technological UniversitySummer 2026 examination
GTU BE03000181 Digital System Design Summer 2026 Question Paper & PDF
B.E. · EC Engineering · Semester 3 · Subject code BE03000181
- Total
- 70 marks
- To pass
- 23 marks (33%)
- Duration
- 2.5 Hours 2:30 PM – 5:00 PM
- Questions
- 5 with internal choice
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3 of 25 questions on this paper were also asked in other years. 1 more is a type of question GTU sets again with new data. Each is marked below with the years it appeared.See all 4 repeated BE03000181 questions, most asked first
Q.2
14 Marks(a)
Draw a 3-input EX-OR gate write its truth table and derive its input-output relationship.
(b)
State and prove De Morgan’s theorems.
(c)
Design a 4-bit binary adder cum subtractor.
OR
Q.3
14 Marks(a)
Define: Resolution, Accuracy, Conversion time.
(b)
Implement a full-addder with smallest size Multiplexer
(c)
simplify the following Boolean function using K-map:
P(A,B,C,D,E,F)=Ʃm(20,28,52,60) and implement using minimum number of logic gates
OR
(a)
Define: Tri-state logic, Maxterm, Minterm
(b)
Implement 2-input EX-OR function by only NAND gates.
(c)
simplify the following Boolean function using tabulation:
P(A,B,C,D,E,F)=Ʃm(20,28,52,60) and implement using minimum number of NOR gates.
Q.4
14 MarksOR
(a)
State the differences between ROM and PROM
(b)
Convert an SR FF to D-FF.
(c)
Design a 3-bit binary ripple counter using T-FF.
Q.5
14 Marks(a)
Show CMOS implantation of F=A.(B+C)
(b)
Implement a full-adder using PROM
(c)
A 4-bit weighted resistor DAC has resistor value of 32 KΩ corresponding to LSB. Determine the Value of other resisters. Input voltage is 5 V. Feedback resistor is 3.2 KΩ. Determine the Value of other resisters Determine the output voltage corresponding to LSB. Also calculate full scale output.
OR
(a)
Show CMOS implantation of F=A+(B.C)
(b)
Implement a full-adder using PLA
(c)
A 4-bit successive Approximation register based ADC has an input of 5.2 V. Show the complete state diagram to reach the final binary output. If 1 MHz clock is used, calculate the time required for the output to settle.
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About this paper
Official Gujarat Technological University (GTU) examination paper for Digital System Design (Summer 2026, B.E. · EC Engineering, Sem 3). Features complete 70-mark regular & remedial examination pattern, official marking distribution across all 5 questions, and direct 1-click official PDF download.
Transcribed for student exam preparation from Gujarat Technological University official examination archives. Questions, syllabus guidelines, and curriculum marking schemes remain the intellectual property of Gujarat Technological University.